Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Defect Analysis and a New Fault Model for Multi-port SRAMs
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reducing register ports for higher speed and lower energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Realistic Fault Models and Test Procedures for Multi-Port SRAMs
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Dynamic Read Destructive Fault in Embedded-SRAMs: Analysis and March Test Solution
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution
ATS '04 Proceedings of the 13th Asian Test Symposium
A Speculative Control Scheme for an Energy-Efficient Banked Register File
IEEE Transactions on Computers
Proceedings of the 42nd annual Design Automation Conference
Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and Characterization
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Architecture exploration for efficient data transfer and storage in data-parallel applications
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
The research of efficient dual-port SRAM data exchange without waiting with FIFO-based cache
WISM'10 Proceedings of the 2010 international conference on Web information systems and mining
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Multi-port SRAMs are often implemented using static random access memory (SRAM) due to its fast operation and the ability to support multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust memories and investigating their failure characteristics become critical. In this paper, we study the defects occurring in the multi-port SRAM cells. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of test patterns. Not only have existing models been taken into account in our simulation but also a new fault model, namely, simultaneous deceptive destructive read fault for the multi-port memory is introduced. In addition, we extend our study to the defect tolerant design of memories by proposing a differential current-mode sense amplifier for 3-port SRAM based register file. We examine the fault models of resistive defects within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defects at 4.6脳 for dual-port read and 5.8脳 for 3-port read compared to voltage-mode sensing with 0.18 μm manufacturing process technology.