Realistic Fault Models and Test Procedures for Multi-Port SRAMs

Authors:
Said Hamdioui;Ad J. van de Goor;David Eastwick;Mike Rodgers
Affiliations:
-;-;-;-
Venue:
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Year:
2001

Citing 0
Cited 2

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Journal of Electronic Testing: Theory and Applications
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009

Quantified Score

Hi-index	0.00

Visualization

Abstract

Abstract: This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults,..., p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of.