Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design and test space exploration of transport-triggered architectures
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
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Testing two-port memories requires the useof single-port tests as well as special two-port tests; thetest strategy determines which tests to be used. Manytwo-port memories have ports which are read-only orwrite-only; this impacts the possible fault models, thetests for single-port and two-port memories, as well asthe test strategy. This paper presents a test strategyfor two-port memories and covers the consequences ofthe port restrictions (read-only or write-only ports).