Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
A New Testing Acceleration Chip for Low-Cost Memory Tests
IEEE Design & Test
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
ATS '00 Proceedings of the 9th Asian Test Symposium
Built-In Self-Test for Multi-Port RAMs
ATS '97 Proceedings of the 6th Asian Test Symposium
An efficient test method for embedded multi-port RAM with BIST circuitry
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
A 5 Gb/s 9-port application specific SRAM with built-in self test
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Detection of Inter-Port Faults in Multi-Port Static RAMs
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
Soft Faults and the Importance of Stresses in Memory Testing
Proceedings of the conference on Design, automation and test in Europe - Volume 2
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with the conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings will be prevented, has been emphasized. Next, the paper presents a methodology to design tests for realistic unique dual-port memory faults, resulting in a set of three linear single-addressing tests which are merged into a single march test (March s2PF), and one linear double-addressing test (March d2PF). March s2PF and March d2PF have been implemented at Intel. The results show that they detect unique faults, i.e., faults that cannot be detected with conventional single-port memory tests. This make them very attractive industrially.