An efficient test method for embedded multi-port RAM with BIST circuitry

Authors:
T. Matsumura
Affiliations:
-
Venue:
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Year:
1995

Citing 0
Cited 2

Simulation-based test algorithm generation and port scheduling for multi-port memories

Proceedings of the 38th annual Design Automation Conference
Efficient Tests for Realistic Faults in Dual-Port SRAMs

IEEE Transactions on Computers

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Abstract

This overview paper discusses sore of the system opportunities and the manufacturing costs of integrating large amounts of logic and memory on a single chip.