Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference on Test and Design Validity
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Synchronous Dynamic Memory Test Construction: A Field Approach
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
A retention-aware test power model for embedded SRAM
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Memory testing in general, and DRAM testing in particular, has become greatly dependent on the modification of stresses (timing, temperature and voltages) in a way that is difficult to justify using the current understanding of memory faults. This paper introduces a new class of fault models (soft faults) based on a special classification of memory faults, that shows why it is fundamentally necessary to apply stresses. The paper calculates the relative probability of soft faults for a specific failure mechanism and compares this probability in DRAMs with that in SRAMs. In addition, the concept of soft faults is validated using defect injection and electrical simulation of a Spice DRAM model.