Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Transparent Memory Testing for Pattern-Sensitive Faults
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
TEST PATH SIMULATION AND CHARACTERISATION
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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The structural complexity and test challenges of complexdependent memory structures are described. An isolationstrategy to minimize the test logic overhead and delay penaltyis presented. A set of custom memory test algorithms isdesigned to test the memory cell, bridging and multi-portfaults in complex dependent memory structures. A novelprogrammable memory BIST architecture to realize the developed custom memory test algorithms has been described.The proposed memory BIST architecture can be used to testthe dependent memory structures in different stages of theirfabrication and assembly. The experimental results demonstrate the area overhead of different components of the proposed programmable memory BIST architecture.