Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications
EDCC-2 Proceedings of the Second European Dependable Computing Conference on Dependable Computing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On the Necessity of On-line-BIST in Safety-Critical Applications - A Case-Study
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
An open notation for memory tests
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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The Transparent Online Memory Test (TOMT)proposed in this paper has been specifically developed for online testing of word-oriented memorieswith parity or Hamming code protection. Using arotated address sequence the algorithm passes fourtimes through the whole address space and performsembedded march tests for every word. The careful interleaving of word-oriented and bit-oriented test allows to attain a fault coverage and a test durationcomparable to the widely used March C- algorithm.The proposed memory test detects all stuck-at faults,all transition faults, all address decoder faults (evenstuck-open address decoder faults), all single couplingfaults (CFs, even write and read disturb CFs) and areasonable percentage of linked CFs. Nevertheless,the algorithm is suitable for online use and can beimplemented in hardware with moderate effort.