Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Error-control coding for computer systems
Error-control coding for computer systems
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Embedded DRAM architectural trade-offs
Proceedings of the conference on Design, automation and test in Europe
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test
Testing a Switching Memory in a Telcommunication System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
Self-Learning Signature Analysis for Non-Volatile Memory Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Exact Aliasing Computation for RAM BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Making DRAM refresh predictable
Real-Time Systems
| Hi-index | 0.00 |
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test characteristic of the memory contents and compare it to a precomputed reference characteristic. Experiments show that the proposed technique significantly reduces the time between the occurence of an error and its detection (error detection latency). It also achieves a very high error coverage at low hardware costs. Therefore it perfectly complements standard on-line checking approaches relying on error detecting codes, where the detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.