Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Microc/OS-II
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip
IBM Journal of Research and Development
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Tightening the Bounds on Feasible Preemption Points
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control
Microelectronics Journal
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
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Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known. While periods are generally derived from the problem specification, a task's code needs to be statically analyzed to derive safe and tight bounds on its WCET. Such static timing analysis abstracts from program input and considers loop bounds and architectural features, such as pipelining and caching. However, unpredictability due to dynamic memory (DRAM) refresh cannot be accounted for by such analysis, which limits its applicability to systems with static memory (SRAM).In this paper, we assess the impact of DRAM refresh on task execution times and demonstrate how predictability is adversely affected leading to unsafe hard real-time system design. We subsequently contribute a novel and effective approach to overcome this problem through software-initiated DRAM refresh. We develop (1) a pure software and (2) a hybrid hardware/software refresh scheme. Both schemes provide predictable timings and fully replace the classical hardware auto-refresh. We discuss implementation details based on this design for multiple concrete embedded platforms and experimentally assess the benefits of different schemes on these platforms. We further formalize the integration of variable latency memory references into a data-flow framework suitable for static timing analysis to bound a task's memory latencies with regard to their WCET. The resulting predictable execution behavior in the presence of DRAM refresh combined with the additional benefit of reduced access delays is unprecedented, to the best of our knowledge.