Dynamic Memory Design for Low Data-Retention Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A Comparative Evaluation of Designs for Reliable Memory Systems
Journal of Electronic Testing: Theory and Applications
Flikker: saving DRAM refresh-power through critical data partitioning
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Block-based multiperiod dynamic memory design for low data-retention power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of hybrid DRAM/PRAM-based main memory
Proceedings of the 48th Design Automation Conference
Making DRAM refresh predictable
Real-Time Systems
RAIDR: Retention-Aware Intelligent DRAM Refresh
Proceedings of the 39th Annual International Symposium on Computer Architecture
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A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) [1-3] to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to insure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100 X) reducing the refresh power. Experimental results of a test system are presented.