Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial BIST of Embedded RAMs
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Area versus detection latency trade-offs in self-checking memory design
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An On-Line BISTed SRAM IP Core
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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The article describes the architecture of a circuit used in a telephone switching unit and focuses on its on-line and off-line test features. Several techniques have been exploited: BIST is adopted to test some embedded memories, Partial Scan allows the test of the remaining logic, and Boundary Scan is used to activate the test and gather the results. Data are reported, concerning the obtained fault coverage, the hardware overhead and the performance penalties introduced by the approach. By sharing the same circuitry for both on-line and off-line testing we succeeded in minimizing the additional logic.