Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test
Online and Offline BIST in IP-Core Design
IEEE Design & Test
A Family of Self-Repair SRAM Cores
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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In digital systems design, strict reliability constraintsusually impose very low fault latency and high degree offault detection of permanent and transient faults. Inparticular, memory modules, as either devices or IP cores,appeared as one of the most critical parts. This paperpresents an advanced on-line memory BIST architectureimplemented as an IP core developed fortelecommunication applications at Italtel SpA, the majorItalian manufacturers of telecom systems. A fault latencyreduction architecture, a code-based fault detectionscheme, and an architecture-based fault avoidance havebeen composed to meet the required reliability constraints.