Increased Throughput for the Testing and Repair of RAMs with Redundancy
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An On-Line BISTed SRAM IP Core
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Memory Defect Tolerance Architectures for Nanotechnologies
Journal of Electronic Testing: Theory and Applications
Utilization of SECDED for soft error and variation-induced defect tolerance in caches
Proceedings of the conference on Design, automation and test in Europe
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In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed On-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed, ranging from an external test to an On-line concurrent BIST.