Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
IBM Journal of Research and Development
Detection of coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using March Tests to Test SRAMs
IEEE Design & Test
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference on Test and Design Validity
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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There are many difficulties inherent in the testing of largeon-chip caches. This paper presents some of theseproblems and provides motivation for solving them. Afterthe motive has been established, the techniques used to testthe PA8500 on-chip caches are described. This isfollowed by a detailed explanation of the test hardware,and an example of how it is used.