Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
IBM Journal of Research and Development
Detection of coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using March Tests to Test SRAMs
IEEE Design & Test
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics
| Hi-index | 0.00 |
The PA7300 was the first PA-RISC microprocessor to incorporate an on-chip cache. To test its 128-Kbyte memory, test hardware was included consisting of an input register, an output MISR, an LFSR address source, and a state machine. The state machine was capable of executing a predefined march test with a fixed address sequence and programmable data pattern. The successes achieved on the PA7300 using this strategy, combined with some of its shortcomings, have lead to the development of a memory test subsystem on Hewlett Packard's next microprocessor, the PA8500.This article describes the memory test hardware on the PA8500, beginning with the requirements that motivated the design. An explanation of the cache architecture is given, and followed by a description of the blocks that make up the memory test subsystem. The final section presents an example that shows how the subsystem can be used to test the memory.