Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Generating March Tests Automatically
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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Given a set of memory array faults the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework.