Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Error-tolerance memory Microarchitecture via Dynamic Multithreading
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Exploiting soft redundancy for error-resilient on-chip memory design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improving error tolerance for multithreaded register files
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.