Error-tolerance memory Microarchitecture via Dynamic Multithreading

Authors:
Lei Wang
Affiliations:
Dept. of Electrical and Computer Engineering University of Connecticut
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

Presented in this paper is an error-tolerance multithreaded register file microarchitecture that employs dynamicmultithreading redundancy for error control. The proposed technique is based on the observation that concurrent threads may not access a register entry simultaneously. The non-overlappedregister access patterns create hardware redundancy dynamically that can be exploited for error control. This significantly improves access time during error recovery. Simulation results of a generic simultaneous multithreading processor on the SPEC CPU2000 benchmark programs demonstrate 13.8% to 50.7% reduction in register read access overheads subject to 2% hardware overheads. The proposed error-tolerance memory microarchitecture features good scalability micro processor generations, where soft errors are expected to get worse with semiconductor process scaling.