Error-tolerance memory Microarchitecture via Dynamic Multithreading
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Exploiting soft redundancy for error-resilient on-chip memory design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improving error tolerance for multithreaded register files
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In certain memory systems the most common error is a single error and the next most common error is two errors in positions which are stored physically adjacent in the memory. In this correspondence we present optimal codes for recovering from such errors. We correct single errors and detect double adjacent errors. For detecting adjacent errors we consider codes which are byte-organized. In the binary case, it is clear that the length of the code is at most 2r-r-1, where r is the redundancy of the code. We summarize the known results and some new ones in this case. For the nonbinary case we show an upper bound, called “the pairs bound,” on the length of such code. Over GF(3) codes with bytes of size 2 which attain the bound exist if and only if perfect codes with minimum Hamming distance 5 over GF(3) exist. Over GF(4) codes which attain the bound with byte size 2 exist for all redundancies. For most other parameters we prove the nonexistence of codes which attain the bound