Extending boundary-scan to perform a memory built-in self-test

Authors:
Henning Bahr;Gordon Russell;Yajian Li
Affiliations:
School of Electrical, Electronic and Computer Engineering, University of Newcastle Upon Tyne, United Kingdom;School of Electrical, Electronic and Computer Engineering, University of Newcastle Upon Tyne, United Kingdom;School of Electrical, Electronic and Computer Engineering, University of Newcastle Upon Tyne, United Kingdom
Venue:
ICC'05 Proceedings of the 9th International Conference on Circuits
Year:
2005

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Abstract

We present a novel test architecture which combines IEEE 1149.1 Boundary-Scan with a Memory Built-In Self-Test. The TDI pin is used for serially shifting in the test data into a test data register which is connected to the memory. The finite state machine of the TAP controller performs the memory test algorithm. The test response is shifted out via the TDO pin for off-chip analyses. The test architecture offers small area overhead, acceptable test time, increased flexibility and analysis capabilities while maintaining compliance to the Boundary-Scan standard.