Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Testing a Switching Memory in a Telcommunication System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
Self-Learning Signature Analysis for Non-Volatile Memory Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST scheme are comparable to the conventional transparent BIST structures. Experimental results show that in many cases the proposed test techniques achieve a higher fault coverage in shorter test time.