Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Designing UltraSparc for Testability
IEEE Design & Test
Alpha 21164 Testability Strategy
IEEE Design & Test
Testing a Switching Memory in a Telcommunication System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
Self-Learning Signature Analysis for Non-Volatile Memory Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Nondestructive RAM Testing by Analyzing the Output Data for Symmetry
Automation and Remote Control
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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