The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Testability Features of the SuperSPARCtm
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testability Strategy of the ALPHA AXP 21164 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Pentium Pro Processor Design for Test and Debug
IEEE Design & Test
Alpha 21164 Manufacturing Test Development and Coverage Analysis
IEEE Design & Test
An object-oriented approach to the concurrent engineering of electronics assemblies
Computers in Industry
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
PENTIUM® PRO PROCESSOR DESIGN FOR TEST AND DEBUG
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Implementing a self-testing 8051 microprocessor
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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We describe the testability strategy and design-for-test features of the Alpha 21164 microprocessor. We discuss the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them.The Alpha 21164 microprocessor is a superscalar implementation of Digital's 64-bit RISC architecture designed to meet the requirements of a wide variety of systems ranging from PC clients to enterprise server systems.