Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
Digital Technical Journal - Special 10th anniversary issue
Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
Digital Technical Journal - Special 10th anniversary issue
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
ACM Transactions on Computer Systems (TOCS)
Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs
ICS '97 Proceedings of the 11th international conference on Supercomputing
Resource widening versus replication: limits and performance-cost trade-off
ICS '98 Proceedings of the 12th international conference on Supercomputing
Integrated predicated and speculative execution in the IMPACT EPIC architecture
Proceedings of the 25th annual international symposium on Computer architecture
Improving the memory-system performance of sparse-matrix vector multiplication
IBM Journal of Research and Development
Quantitative Evaluation of Register Pressure on Software Pipelined Loops
International Journal of Parallel Programming
Using value prediction to increase the power of speculative execution hardware
ACM Transactions on Computer Systems (TOCS)
Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Performance analysis of the Alpha 21264-based Compaq ES40 system
Proceedings of the 27th annual international symposium on Computer architecture
Compatible cell connections for multifamily dynamic logic gates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Alpha 21164 Testability Strategy
IEEE Design & Test
VIS Speeds New Media Processing
IEEE Micro
IEEE Micro
The Alpha 21264 Microprocessor
IEEE Micro
Increasing hardware data prefetching performance using the second-level cache
Journal of Systems Architecture: the EUROMICRO Journal
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Register File Design Considerations in Dynamically Scheduled Processors
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
A Statistically Rigorous Approach for Improving Simulation Methodology
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Timed Petri net models of multithreaded multiprocessor architectures
PNPM '97 Proceedings of the 6th International Workshop on Petri Nets and Performance Models
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
An enhanced DLX-based superscalar system simulator
WCAE-3 '97 Proceedings of the 1997 workshop on Computer architecture education
Evaluating the performance of dynamic branch prediction schemes with BPSim
WCAE-3 '97 Proceedings of the 1997 workshop on Computer architecture education
Idempotent processor architecture
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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The 21164 is a new quad-issue superscalar Alpha microprocessor. This new high-performance chip can execute 1.2 billion instructions per second. The part became available in January of 1995 and delivered SPECint92/SPECfp92 performance of 335/500 (estimated), performance unmatched by other commercially available microprocessors. It is implemented in 0.5 micron CMOS and the CPU clock speed is 300 MHz. Instruction execution is controlled by the quad-issue superscalar instruction unit. There are two 64-bit integer execution pipelines and two 64-bit floating-point pipelines. Memory instructions are initiated in the integer pipelines and are completed by the memory and bus interface units that together implement a high-throughput memory subsystem employing a multi-level cache hierarchy.