Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Improving the accuracy of dynamic branch prediction using branch correlation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Tuning the Pentium Pro Microarchitecture
IEEE Micro
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
Optimal 2-Bit Branch Predictors
IEEE Transactions on Computers
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
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BPSim (Branch Prediction Simulator) is a trace-driven simulator for predicting branch outcomes in high performance processors. It incorporates various dynamic prediction schemes widely reported in the literature and practiced in existing processors such as the MIPS R10000, Pentium Pro and Alpha 21164 [1, 10, 13]. Users can benefit from the completeness and flexibility of this simulator in gaining an understanding of the trade-off between prediction accuracy and hardware cost especially in an education environment.