Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Modern VLSI design: a systems approach
Modern VLSI design: a systems approach
Alpha 21164 Testability Strategy
IEEE Design & Test
Clock controller design in SuperSPARC II microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Testability features of the MC68060 microprocessor
ITC'94 Proceedings of the 1994 international conference on Test
A case-study in the use of scan in microSPARCTM testing and debug
ITC'94 Proceedings of the 1994 international conference on Test
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents a simple but elegant approach to effectivelyautomate the time-consuming silicon debug procedurefor microprocessor embedded memory arrays thatallow no direct test modes, based on sequential ATPG withbuilt-in design-for-debug methodology.