The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automatic Timing Margin Failure Location Analysis by CycleStretch Method
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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RISC processors including microSPARC™ are becoming increasingly complex and are requiring more device expertise on the part of the test engineer. At the same time, the increasing complexity and sophistication of VLSI/ULSI testers also require higher levels of tester expertise. It is difficult, if not impossible for today's test engineer to keep up with new testers every two to three years while trying to attain design level knowledge necessary to test and debug leading edge processors. This paper describes techniques by which a test engineer can, while treating the processor as a black box, proceed efficiently through the debug process up to the point of final circuit analysis. This paper describes the various techniques used, providing examples of actual device data, both pre and post debug.