IEEE Design & Test
Designing UltraSparc for Testability
IEEE Design & Test
Alpha 21164 Testability Strategy
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
DFT Strategy for Intel Microprocessors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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This paper describes the Design for Test (DFT) and silicondebug features of the Pentium® Pro processor, and itsproduction test development methodology. The need toquickly ramp a complex, high-performance microprocessorinto high-volume manufacturing with low defect rates ledthe design team to a custom low-area DFT approach,coupled with a manually-written test methodology whichtargeted several fault models. Results show that thisapproach was effective in balancing testability needs withother design constraints, while enabling excellent time tomarket and test quality.