Discrete logarithms in finite fields and their cryptographic significance
Proc. of the EUROCRYPT 84 workshop on Advances in cryptology: theory and application of cryptographic techniques
Discrete logarithms: a parallel pseudorandom pattern generator analysis method
Journal of Electronic Testing: Theory and Applications
Alpha 21164 Testability Strategy
IEEE Design & Test
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fast and Low-Area TPGs Based on T-Type Flip-Flops can be Easily Integrated to the Scan Path
ETW '00 Proceedings of the IEEE European Test Workshop
On Using Deterministic Test Sets in BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Test Pattern Generator Design Optimization Based on Genetic Algorithm
IEA/AIE '08 Proceedings of the 21st international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: New Frontiers in Applied Artificial Intelligence
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In the paper authors analyse properties of the various structures of linear registers (LFSRs) that are used as the test pattern generators in VLSI circuits. It is shown that the majority of them have one or more of the following drawbacks: • large area overhead that is caused by the large number of XOR gates, • reduced operational frequency due to presence of the long connection in the main feed-back loop and the high fan-out on the outputs of the flip-flops, • inflexible structure that cannot be easily redesigned and adjusted to the needs of the digital circuit efficient testing. In the paper we present a new type of LFSR that is free from all mentioned above disadvantages. We also develop the algebraic description of its operation and the methods of its designing. Finally we give numerous examples of its structures for different lengths of the register.