Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.01 |
The test pattern generators (TPG) in BIST usually generate pseudorandom patterns and after the pseudorandom testing phase additional deterministic test vectors, which can be compressed by the means of the same TPG, detect the random resistant faults. Another possibility is to optimize the TPG structure so that the generated test set contains all the necessary deterministic test vectors, which detect hard-to-test faults. The vectors are obtained by the means of TPG output modifications. This approach is not acceptable for large circuits because of additional delay caused by the output combinational logic. We have proposed a TPG that has a very simple structure and in which the patterns covering the random resistant faults are generated by the TPG without any output modifying logic. XORing the pre-computed modifying bits with one of the TPG internal flip-flop input controls the TPG sequence. Finding the modifying bits is done by an own algorithm, which optimizes the fault coverage gain, which is obtained by each of the generated test vectors. Several experiments were done with the ISCAS 85 and 89 benchmark circuits. The storage capacity needed for storing the modifying bits of the exercised circuits is low while the test application time is short.