Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST

Bit-flipping BIST

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

STARBIST: scan autocorrelated random pattern generation

DAC '97 Proceedings of the 34th annual Design Automation Conference

Scalable Test Generators for High-Speed Datapath Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing

Mixed-Mode BIST Using Embedded Processors

Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing

Test of future system-on-chips

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

On Using Twisted-Ring Counters for Test Set Embedding in BIST

Journal of Electronic Testing: Theory and Applications

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

Journal of Electronic Testing: Theory and Applications

Test Set Embedding Based on Phase Shifters

EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing

An algorithmic approach to optimizing fault coverage for BIST logic synthesis

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Accumulator based deterministic BIST

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A Ring Architecture Strategy for BIST Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

Efficient Test Mode Selection & Insertion for RTL-BIST

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Scan Encoded Test Pattern Generation for BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Using Machine Learning for Logic BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Test Width Compression for Built-In Self Testing

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Using Deterministic Test Sets in BIST

IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)

A BIST Pattern Generator Design for Near-Perfect Fault Coverage

IEEE Transactions on Computers

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

Journal of Electronic Testing: Theory and Applications

Hybrid BIST optimization using reseeding and test set compaction

Microprocessors & Microsystems

Improving linear test data compression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Operating system scheduling for efficient online self-test in robust systems

Proceedings of the 2009 International Conference on Computer-Aided Design