Scan Encoded Test Pattern Generation for BIST

  • Authors:
  • Kun-Han Tsai;Janusz Rajski;Malgorzata Marek-Sadowska

  • Affiliations:
  • -;-;-

  • Venue:
  • ITC '97 Proceedings of the 1997 IEEE International Test Conference
  • Year:
  • 1997

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Abstract

This paper presents an improved scan-based BISTscheme which achieves very high fault coverage withoutany modification of the mission logic, i.e. no test pointinsertion, no test data to store and very simple BIST hardwarewhich does not depend on the size of the circuit. Theapproach utilizes scan order and its polarity in scan synthesis,effectively converting it into a ROM encoding a fewtest vectors which serve as centers of clusters from whichthe other vectors are derived by complementing at randomtheir coordinates. The proposed method successfully teststhe random pattern resistant faults, which is the major problemof traditional LFSR-based BIST, with lower hardwarecost and more efficient algorithm than previous one. Experimentalresults demonstrate that a very high fault coveragecan be achieved with much smaller test set than other pseudorandompattern generation methods published so far.