Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the design of optimal counter-based schemes for test set embedding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Pattern Generator Design Optimization Based on Genetic Algorithm
IEA/AIE '08 Proceedings of the 21st international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: New Frontiers in Applied Artificial Intelligence
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In this paper we present a new method for designing test pattern generators (TPG) for the embedding of precomputed test sets. The proposed TPG is based on the use of an LFSR and phase shifters and produces the exact test set. The proposed TPG compares favorably, with respect to test application time and/or hardware overhead, to the already known approaches.