Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
FPL Based Self-Test with Deterministic Test Patterns
Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping
WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
Test Set Embedding Based on Phase Shifters
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
Efficient Multiphase Test Set Embedding for Scan-based Testing
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reliability considerations in mobile devices
Proceedings of the 3rd international conference on Mobile multimedia communications
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We propose a very simple and fast CAD tool to check whether a binary counter can reproduce a predetermined set of test patterns in a reasonable time. Given a test matrix T, the tool uses column merging, complementation, and permutation so that the distance between the starting and the finishing vector of the corresponding counter is minimized. The hardware overhead of the proposed approach is by far lower than that of any other existing approach. Although it is computationally difficult (NP-hard) to obtain the absolute minimum distance, we present an algorithm which in the absence of don't cares in the test matrix, finds an appropriate column merging, complementation, and permutation that guarantees the distance is never more than twice as large as the best possible. In the presence of don't cares, the latter algorithm forms the basis of a powerful heuristic. Experiments on various test sets on benchmark circuits show that the exact number of clock cycles needed for a binary counter to reproduce all the patterns for the hard-to-detect faults compares favorably with the expected number yielded by existing Weighted Random LFSR-based approaches which have significantly higher hardware overhead.