On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
Reseeding-Based Test Set Embedding with Reduced Test Sequences
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the design of optimal counter-based schemes for test set embedding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set embedding for deterministic BIST using a reconfigurable interconnection network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiphase BIST: a new reseeding technique for high test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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In this paper a new test set embedding method with reseeding for scan-based testing is proposed. The bit sequences of multiple cells of an LFSR, which is used as test pattern generator, are exploited for effectively encoding the test set of the core under test (multiphase architecture). A new algorithm which comprises four heuristic criteria is introduced for efficiently selecting the required seeds and LFSR cells. Also, a cost metric for assessing the quality of the algorithm's results is proposed. By using this metric, the process of determining proper values for the algorithm's input parameters is significantly simplified. The proposed method compares favorably with the most recent and effective test set embedding techniques in the literature.