An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST

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ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Year:
2002

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Abstract

In this paper we propose a new algorithm for seeds selection in LFSR-based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.