Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
Exploiting BIST Approach for Two-Pattern Testing
ATS '98 Proceedings of the 7th Asian Test Symposium
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
ETW '00 Proceedings of the IEEE European Test Workshop
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On Using Efficient Test Sequences for BIST
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
IEICE - Transactions on Information and Systems
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
On-line control flow error detection using relationship signatures among basic blocks
Computers and Electrical Engineering
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Electrical Engineering
Built-in test for CMOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Cellular automata-based pseudorandom number generators for built-in self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test responses compaction in accumulators with rotate carry adders
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned operations. In order to detect faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed requires two-pattern tests. In this paper a novel two-pattern test generator for Arithmetic BIST is presented. Its hardware implementation compares favorably to the techniques that have been presented in the literature. Application of the proposed scheme for the two-pattern testing of ROM modules revealed that the testing of small-to-medium size ROMs is completed within reasonable time and with negligible hardware overhead.