Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Selection of Efficient Arithmetic Additive Test Pattern Generators
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
Accumulator-Based Weighted Pattern Generation
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Diophantine-Equation Based Arithmetic Test Set Embedding
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
On the design of optimal counter-based schemes for test set embedding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.