IEEE Transactions on Computers - Special issue on fault-tolerant computing
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Methodology to Design Efficient BIST Test Pattern Generators
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Point Insertion for an Area Efficient BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Generating deterministic unordered test patterns with counters
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
On Control Memory Minimization in Microprogrammed Digital Computers
IEEE Transactions on Computers
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We present a method for designing test generatorcircuits (TGCs) that incorporate a precomputed testset TD in the patterns they produce. Our methoduses width compression based on the property of d-compatibles, which allows us to encodeTD more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists ofcounter, which generates a set of encoded test patterns, and a decompression circuit consisting of simplebinary decoders that generate a final sequence containing TD. These TGCs are applicable to embedded-corecircuits whose detailed designs are not available. Wedemonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS 89 benchmark circuits.