A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
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We study the behavior of counter-based schemes as very low hardware overhead built-in mechanisms for reproducing unordered test patterns. We show that a small number of seeds, each defining a test pattern generation session, can result in an economical design in terms of both time and hardware. We present counter-based schemes with a trade-off on the time and hardware overhead. Experimental results on the ISCAS'85 benchmarks and comparisons with other built-in mechanisms show that the proposed schemes constitute a promising technique for effective built-in deterministic test pattern generation.