A Methodology to Design Efficient BIST Test Pattern Generators

Scalable Test Generators for High-Speed Datapath Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation

IEEE Transactions on Computers

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

Journal of Electronic Testing: Theory and Applications

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

Journal of Electronic Testing: Theory and Applications

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers

MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults

ITC '00 Proceedings of the 2000 IEEE International Test Conference

A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Test Width Compression for Built-In Self Testing

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

IEEE Transactions on Computers

A BIST Pattern Generator Design for Near-Perfect Fault Coverage

IEEE Transactions on Computers

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Antirandom testing: a distance-based approach

VLSI Design