Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing and testable design of high-density random-access memories
Testing and testable design of high-density random-access memories
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Towards a Uniform Notation for Memory Tests
EDTC '96 Proceedings of the 1996 European conference on Design and Test
The repeated nondestructive march tests with variable address sequences
Automation and Remote Control
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For the nondestructive march memory testing based on the symmetry analysis of the read out flows of output data, consideration was given to the conditions for manifestation of the bit-stuck, transition, and coupling faults and to construction of algorithms providing their hundred-percent covering by a minimum-complexity test and its minimum-complexity hardware realization.