Roving Emulation as a Fault Detection Mechanism
IEEE Transactions on Computers
IEEE Transactions on Computers
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
A Statistical Theory of Digital Circuit Testability
IEEE Transactions on Computers
A branching process model for observability analysis of combinational circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
Concrete Math
WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
STAFAN: An alternative to fault simulation
DAC '84 Proceedings of the 21st Design Automation Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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Fault coverage and test length estimation in circuits under random test is the subject of this paper. Testing by a sequence of random input patterns is viewed as sequential sampling of faults from a given fault universe. Based on this model, the probability mass function ($\mbi{pmf}$) of fault coverage and expressions for all its moments are derived. This provides a means for computing estimates of fault coverage as well as determining the accuracy of the estimates. Test length, viewed as waiting time on fault coverage, is analyzed next. We derive expressions for its $\mbi{pmf}$ and its probability generating function ($\mbi{pgf}$). This allows computation of all the higher order moments. In particular, expressions for mean and variance of test length for any specified fault coverage are derived. This is a considerable enhancement of the state of the art in techniques for predicting test length as a function of fault coverage. It is shown that any moment of test length requires knowledge of all the moments of fault coverage, and hence, its $\mbi{pmf}$. For this reason, expressions for approximating its expected value and variance, for user specified error bounds, are also given. A methodology based on these results is outlined. Experiments carried out on several circuits demonstrate that this technique is capable of providing excellent predictions of test length. Furthermore it is shown, as with fault coverage prediction, that estimates of variances can be used to bound average test length quite effectively.Index Terms驴Fault coverage, test length, urn models, occupancy, waiting time.