Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Industrial BIST of Embedded RAMs
IEEE Design & Test
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
| Hi-index | 4.10 |
Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future.