Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
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This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.