A Performance Model for Run-Time Reconfigurable Hardware Accelerator

Authors:
Gang Wang;Du Chen;Jian Chen;Jianliang Ma;Tianzhou Chen
Affiliations:
ZJU-INTEL Technology Center College of Computer Science, Zhejiang University, Zhejiang, P.R. China;ZJU-INTEL Technology Center College of Computer Science, Zhejiang University, Zhejiang, P.R. China;ZJU-INTEL Technology Center College of Computer Science, Zhejiang University, Zhejiang, P.R. China;ZJU-INTEL Technology Center College of Computer Science, Zhejiang University, Zhejiang, P.R. China;ZJU-INTEL Technology Center College of Computer Science, Zhejiang University, Zhejiang, P.R. China
Venue:
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Year:
2009

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Abstract

The reconfigurable devices such as CPLD and FPGA become more popular for its great potential on accelerating applications. They are widely used as an application-specified hardware accelerator. Many run-time reconfigurable platforms are introduced such as the Intel® QuickAssist Technology. However, it's time consuming to design a hardware accelerator while the performance is hard to determine because of the extra overheads it involved. In order to estimate the efficiency of the accelerator, a theoretical analysis of such platforms was done in our paper. Three factors which impact the performance of the accelerator were concluded as well: speed up ratio, reconfiguration overhead and communication overhead. Furthermore, a performance model was established and an experiment on bzip2 was done to verify the model. The results showed that the model's estimation is very close to the real world and the average error on the efficiency's threshold is less than 5%.