Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of reconfigurable units in superscalar processors
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The first real operating system for reconfigurable computers
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Protected, user-level DMA for the SHRIMP network interface
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Incorporating Memory Management into User-Level Network Interfaces
Incorporating Memory Management into User-Level Network Interfaces
Programmable Stream Processors
Computer
Virtual memory window for application-specific reconfigurable coprocessors
Proceedings of the 41st annual Design Automation Conference
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
An Execution Environment for Reconfigurable Computing
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A Performance Model for Run-Time Reconfigurable Hardware Accelerator
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Runtime multitasking support on polymorphic platforms
ACM SIGARCH Computer Architecture News
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
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We present HybridOS, a set of operating system extensions for supporting fine-grained reconfigurable accelerators integrated with general-purpose computing platforms. HybridOS specifically targets the application integration, data movement and communication overheads for a CPU/accelerator model when running a commodity operating system. HybridOS provides a simple API for applications and a well-defined hardware interface for reconfigurable accelerators. The goal is to reduce the difficulty in mapping applications into a CPU/accelerator model compared to an unrestrained FPGA platform while achieving whole-application speedups. HybridOS is integrated into a full Linux distribution running on the embedded processor of an FPGA. Application-specific accelerators are implemented in the reconfigurable fabric of the FPGA that are allocated to user applications running on Linux. We have developed and evaluated four methods for accessing the data buffers required by hardware-accelerated applications using our prototype. The results of our work show the feasibility of our system for a case study, JPEG encoding with two accelerators, and an evaluation of HybridOS for varying data movement requirements that can be used as a guide for future applications developers