A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Standards for system-level design: practical reality or solution in search of a question?
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Automatic generation of embedded memory wrapper for multiprocessor SoC
Proceedings of the 39th annual Design Automation Conference
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Managing a Reconfigurable Processor in a General Purpose Workstation Environment
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
IEEE Design & Test
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HybridOS: runtime support for reconfigurable accelerators
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Building heterogeneous reconfigurable systems with a hardware microkernel
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A platform for mixed HW/SW algorithm specifications for the exploration of SW and HW partitioning
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. Another obstacle is the lack of portability across different systems. In this work, we present a virtualisation layer consisting of an operating-system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system. Since the virtualisation layer components hide physical details of the system, user designed hardware and software become perfectly portable. A reconfigurable SoC running Linux is used to prove the viability of the concept. Two applications are ported to the system for testing the approach, with their critical functions mapped to the specific coprocessors. We show a significant speedup compared to the software versions, while limited penalty is paid for virtualisation.