A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Operating System Concepts
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Virtual memory window for application-specific reconfigurable coprocessors
Proceedings of the 41st annual Design Automation Conference
Compiler-driven FPGA-area allocation for reconfigurable computing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Chameleon: operating system support for dynamic processors
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
MORP: makespan optimization for processors with an embedded reconfigurable fabric
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Reconfigurable processor hybrids are becoming an accepted solution in the embedded systems domain, but have yet to gain acceptance in the general purpose workstation domain. One problem with current solutions is their lack of support for the dynamic workloads and resource demands of a general purpose workstation. In this paper we describe and demonstrate a reconfigurable processor architecture that lets the operating system dynamically share the FPL resource between a set of applications without the management overheads negating the benefit of having the extra resource.